Systematic Methodology of Mapping Signal Processing Algorithms into Arrays of Processors

Nowadays high speed signal processing has become the only alternative in modern communication system, given the rapidly growing microelectronics technology. This high speed, real time signal processing depends critically both on the parallel algorithms and on parallel processor technology. Special purpose array processor structures will have become the real possibility for high speed signal processing in the next few years. Most signal processing algorithms have built in recursivity and regularity and in for the case of parallel arrays, local connectivity. The availability of such low cost devices, where the parallelpipelined computing represents the main limitation on application, has opened up a new possibility for the implementation of advanced and sophisticated algorithms and VLSI structures. The main advantage of VLSI array processors is the increased rate of throughput required by present–day real time signal processing applications. The answer to this challenge lies in the development of techniques for algorithm analysis, dependency analysis, mapping techniques of the algorithms onto massive parallel array structures, appropriate VLSI design techniques of the systolic arrays, in the partitioning technique and in Digital Signal Processing (DSP) applications. The application domain of such array processors covers different areas, including digital filtering, spectrum estimation, adaptive signal processing, image processing, medical image processing, seismic processing, etc. In the paper we intend to present an overview of the basic mapping procedure with some applications from the area of 1D and 2D signal processing. After a short introduction of systolic processor arrays, the importance of high–speed linear algebra computations is highlighted from the aspect of digital signal processing problems. Section 3 contains the main results of the paper (systematic methodology of transforming an algorithm into systolic array architecture); first the mapping technique of sequential algorithms onto suitable array architecture is proposed, through index set extension and data broadcast (Affine dependencies) elimination, then a procedure is proposed to map the parallelised algorithm into VLSI systolic array architecture. Further in the section, the proposed method is applied on some basic linear algebra algorithms applicable in DSP. Finally, in section 4 DSP implementations will be presented including the simulation results of notch filter and of two– dimensional FIR adaptive filter based on LS SVD algorithm.